The present invention relates to semiconductor chip carriers.
A large-sized computer, for example, may be constituted by a plurality of modules, each including a plurality of leadless chip carriers. Generally, each module has one semiconductor chip mounted thereon.
FIG. 1 schematically illustrates a computer module which includes a plurality of semiconductor chips 1 which are mounted on the corresponding leadless chip carriers 2 which are, in turn, mounted on an insulating module baseplate 3 which has an inter-layer connection conductor layer for electrical connection to the semiconductor chips.
Each leadless chip carrier 2 has, for example, a cross-sectional configuration as macroscopicaally shown in FIGS. 2A and 2B. An insulating substrate 4 made of, for example, a ceramic has one or more through holes 10 in which corresponding conductors 11 are formed by filling, by printing, an electrically conductive material made of, for example, a paste which mainly consists of tungsten and sintering the conductive material together with the substrate. A registration layer 5 made of a metal film, for example, aluminum, is formed on a surface of each of the conductors 11 in the substrate 4 (through hole conductors 11) by sputtering, vapor deposition or the like. A required number of layers of insulating films 6 and inter-layer connection conductor layers 7 are laminated sequentially on the registration layer 5. The formation of the insulating films 6 may be made, for example, by spin coating. The formation of the inter-layer connection conductor layers 7 may be made, for example, by sputtering. The semiconductor chips 1 are connected, for example, by CCB (Controlled Collapse Bonding) solder 9 on the uppermost connection conductor layer 8. Metal plating may be made on the surface of the through hole conductors 11 to improve the adhesiveness to the registration layer 5.
FIG. 3 illustrates a process for manufacturing leadless chip carriers 2. A ceramic substrate 4 in which through holes 10 filled with conductor paste 11 are formed is sintered (step 3-1), a registration layer 5 is formed (step 3-2), a required number of insulating films 5 and inter-layer connection conductor layers 7 are laminated on the registration layer 5 (steps 3-3, 3-4), and, lastly, uppermost connection conductor layer 8 is formed (step 3-5 ).
JP-A-63-19896 published Jan. 27, 1988 discloses a multilayer connection substrate which includes a ceramic multilayer connection conductor substrate having conductors formed on a surface of the substrate and in the substrate and a multilayer circuit formed on the substrate and including connection conductors connected to the former conductors.
JP-A-60-10698 published Jan. 19, 1985 discloses a multilayer connection substrate formed by polishing a surface of a ceramic substrate having through hole connection conductors therein and flattening exposed portions of the through hole connection conductors, covering the flattened surface with metal protective films, and forming a multilayer connection conductor layer which connects to the through hole connection conductors on the surface of the ceramic substrate thus obtained.
In a module which uses such a chip carrier as schematically shown in FIG. 2B, while the through hole conductors 11 mainly serve as a power supply line or a signal line, a decrease in the power source voltage for the IC circuit devices in the semiconductor chip 1, fluctuations of signals in the IC circuit devices, etc., sometime occur heretofore, suppression of such phenomena has been required.